The present invention relates to a block partitioned dynamic random access semiconductor memory array, and more particularly, to a method of and circuitry for generating timing signals to stagger restoration therein for reducing peak current consumption of the array.
2. Description of the Prior Art
In the conventional dynamic type MOS.RAM (metal oxide semiconductor.random access memory), consumed current in an active cycle is not averaged, so that several sharp peaks appear in one cycle. Referring now to FIGS. 1 to 3, such a conventional example is described.
FIG. 1 is a block diagram showing a structure of the conventional Block Partitioned dynamic type MOS.RAM (1M bits). The Block Partitioned DRAM is described in, for example, "A 60ns 256K.times.1 Bit DRAM Using LD.sup.3 Technology and Double-Level Metal Interconnection", IEEE Journal of Solid-States Circuits, Vol. SC-19. No. 5, October 1984, p. 585. In FIG. 1, a memory cell array MA is divided into, for example, four blocks #1 to #4. The blocks comprise column decoders CD, respectively. The blocks are provided with a common row decoder RD. Each of the blocks in the memory cell array MA is accessed by address signals A0 to A9 (including row addresses RA0 to RA9 and column addresses CA0 to CA9) inputted externally in a time divisional manner. The address signals A0 to A9 are stored in advance in an address buffer AB and then, applied to the row decoder RD and the column decoders CD. The row address RA9 is applied to each of the blocks separately from the other address signals. The row address RA9 selects two blocks where data are to be read or written. For example, when RA9 equals 0, the blocks #1 and #3 are selected. When RA9 equals 1, the blocks #2 and #4 are selected. The row address signals RA0 to RA8 other than RA9 are applied to the row decoder RD, so that any of word lines in each of the blocks is selected. Thus, if the address signals A0 to A9 are externally inputted, any word line in each of the blocks is selected and rises, irrespective of whether or not the particular block is selected by the row address signal RA9. More specifically, a single corresponding word line rises in each of the blocks #1, #2, #3 and #4. This is because a memory cell connected to each of the word lines is refreshed even in the block where data are neither read out nor written. An RAS buffer RB outputs various control signals WL, .PHI..sub.S, .PHI..sub.S in response to a row address strobe signal RAS externally inputted and applies the same to the memory cell array MA. A CAS buffer CB applies to a data input buffer DIB and a data output buffer DOB a signal for controlling input/output of data in response to a column address strobe signal CAS externally inputted. The data input buffer DIB and the data output buffer DOB are connected to the blocks #1 to #4 through a pair of data lines I/O and I/O. The data input buffer DIB temporarily stores data Din externally inputted. The data output buffer DOB temporarily stores data read out from the memory cell array MA and outputs the same to the exterior as output data Dout. A WE buffer WB controls a read mode and a write mode in each of the data input buffer DIB and the data output buffer DOB in response to a write enable signal WE externally inputted.
FIG. 2 is a diagram showing a structure of any of the blocks #1 to #4 shown in FIG. 1. In FIG. 2, a plurality of word lines 1 and a plurality of pairs of bit lines BL and BL (only a pair of bit lines is illustrated in FIG. 2) are provided orthogonal to each other. Memory cells MC each comprising, for example, a single MOSFET and a single capacitor are arranged at intersections of each of the word lines 1 and each of the bit line pairs BL and BL. Each of the word lines 1 is connected to word line driving circuit 2. The word line driving circuit 2 raises the potential on the word line 1 selected by the row decoder RD when the word line driving signal WL is applied from the RAS buffer RB shown in FIG. 1. A restore circuit RS comprising two P channel MOSFETs and a sense amplifier SA comprising two N channel MOSFETs are provided for each of the bit line pairs BL and BL. The sense amplifier SA detects the potentials on the bit lines BL and BL after a memory cell MC is selected and causes the potential on the bit line at a low level to be a ground level. The restore circuit RS pulls up the potential at a high level to a power-supply voltage Vcc. The restore circuits RS each provided for each of the bit line pairs are connected to each other and connected to the power-supply voltage Vcc through a P channel MOSFET 3. The P channel MOSFET 3 has a gate electrode receiving a restore circuit driving signal .PHI..sub.S from the RAS buffer RB. The restore circuits RS each provided for each of the bit line pairs and the P channel MOSFET 3 constitute a restoring system. In addition, the sense amplifiers SA each provided for each of the bit line pairs are connected to each other and connected to a ground through an N channel MOSFET 4. The N channel MOSFET 4 has a gate electrode receiving the sense amplifier driving signal .PHI..sub.S from the RAS buffer RB. The sense amplifiers SA each provided for each of the bit line pairs and the N channel MOSFET 4 constitute a sense amplifier system. Furthermore, one of the bit lines BL in each of the bit line pairs is connected to the data line I/O through an N channel MOSFET 5 and the other bit line BL is connected to the data line I/O through an N channel MOSFET 6. Each of the N channel MOSFETs 5 and 6 has a gate electrode receiving a corresponding decoded output from the column decoder CD.
Furthermore, the bit lines BL and BL are connected to a bit line precharging line 9 through N channel MOSFETs 7 and 8, respectively. A voltage V.sub.BL which is a half of the power supply voltage Vcc is applied to the bit line precharging line 9. Each of the MOSFETs 7 and 8 has a gate terminal receiving a precharge clock .PHI..sub.EQ. In addition, the precharge clock .PHI..sub.EQ is also applied to a gate terminal of an N channel MOSFET 10 interposed between the bit lines BL and BL.
FIG. 3 is a timing chart for explaining operation of the conventional circuit shown in FIGS. 1 and 2. Referring now to FIG. 3, description is made on operation in one cycle of the above described conventional circuit.
The row address strobe signal RAS falls, so that an active period is started. The row address strobe signal RAS defines a non-active period and the active period. The word line 1 specified by the row addresses RA0 to RA8 rises and a signal voltage corresponding to memory cell data appears on the bit line pairs BL and BL. Thereafter, the sense amplifier driving signal .PHI..sub.S rises, so that the sense amplifier system operates. Therefore, the potential on the bit line at a lower potential, of the bit line pairs BL and BL becomes a ground potential. Thereafter, the restore circuit driving signal .PHI..sub.S falls, so that the restoring system operates. Therefore, the potential on the bit line at a higher potential, of the bit line pairs BL and BL is pulled up to the power-supply voltage Vcc. Thereafter, the column decoder CD operates in response to the column addresses CA0 to CA9 latched at the falling time of the column address strobe signal CAS. As a result, the selected bit line pairs BL and BL are connected to the pair of data lines I/O and I/O, so that data are inputted or outputted. When one cycle is completed and the row address strobe signal RAS rises, the selected word line falls and the MOSFETs 7, 8 and 10 are turned on by a precharge signal .PHI..sub.EQ, so that each of the bit line pairs BL and BL is precharged to be the voltage V.sub.BL.
Consumed current Icc applied from a power supply is now considered based on operation in such one cycle. As shown in FIG. 3, the consumed current Icc has five peaks P1 to P5. The peaks P1 to P5 are as follows:
P1: consumed current at the time of generating a clock of a RAS system PA0 P2: bit line charging current at the time of generating a clock in sensing operation and at the time of restoring operation PA0 P3: consumed current at the time of generating a clock of a CAS system PA0 P4: consumed current at the time of generating a clock of a RAS system PA0 P5: consumed current at the time of generating a clock of a CAS system.
More particularly, in a recent system that a peripheral circuit portion comprises a CMOS (complementary metal oxide semiconductor), the row decoder RD and the column decoder CD comprise static circuits and bit lines are precharged to the potential of Vcc, the peak P2 is much larger than the other peaks, which put a load on a power supply system.
Since the conventional semiconductor memory device has the above described structure, the peak value of the consumed current generated at the time of restoration is large, so that a load on the power supply system is large. Thus, particularly, in a DRAM having large capacitance such as 1M bit, the size of the power supply system is increased and the calorific value is increased.
A method for reducing peak current consumption at the time of precharging bit lines is described in the above described document and an article "A 59ns 256K DRAM Using LD.sup.3 Technology and Double Level Metal" ISSCC '84 Dig. Tech Papers, pp. 96. However, the method fails to reduce peak current consumption at the time of restoring operation.
Meanwhile, one of the inventors of the present invention has proposed that restoring operation is started at different timing with a predetermined time difference every block to reduce peak current consumption caused at the time of restoring operation, in a co-pending U.S. application Ser. No. 929,371, filed Nov. 12, 1986.